Many software tools allow electronic designs to be assembled, simulated, debugged, and translated into hardware. In particular this can be done in a high level abstract environment known as a high level modeling system (HLMS), such as the System Generator HLMS from Xilinx, Inc. of San Jose, Calif. In an HLMS the focus is on automation and convenience. Testing, debugging, and hardware generation are done inside the tool. Signal types are flexible (e.g., signed/unsigned fixed precision real/complex numbers, elements of finite fields, etc.), and adjust automatically to accommodate changes in the design. Details of implementation are only presented implicitly. Blocks are polymorphic and translate automatically into efficient hardware implementations. Bit and cycle-true simulation results in the HLMS guarantee that what is seen at the head of the stream faithfully reflects what is seen in hardware.
A design in an HLMS is usually organized as a collection of objects called “blocks.” A block may contain other blocks, in which case the contained blocks are known as “subblocks” or “children” of the container block. The container block is the “parent” of its subblocks. No block may be a subblock of more than one block. A block that has no subblocks is a “leaf,” and blocks that have subblocks are “nonleaves.” Ordinarily, exactly one block is not a subblock of a larger block. This block is known as the “roof” or the “top level” of the design. Blocks represent electronic objects that consume and transform values produced by other blocks, and produce values to be consumed and transformed by other blocks. Lines of communication between blocks are referred to as “signals.” The connection point between a signal and a block is called a “port.”
The portion of an HLMS that translates a design into hardware is called the “netlister”, and the translation process is known as “netlisting.” Usually, the result the netlister produces is expressed in a hardware description language (HDL) such as VHDL or Verilog. VHDL designs are built from objects called “entities.” Similarly, Verilog designs are built from “modules”. For simplicity, such objects are referred to in this document as entities regardless of the specific HDL.
Entities are in many ways similar to HLMS blocks. In particular, entities can, in effect, be built from smaller entities in much the same way that blocks can be built from subblocks. The most straightforward way to netlist an HLMS design is to produce entities whose organization directly mirrors that of the blocks in the design. To do this, the netlister translates “rank-0” blocks into entities, then rank-1, rank-2, and so on. The “rank” of a leaf block is defined to be rank-0, and the rank of a nonleaf is 1+r, where r represents the maximum rank of the block's subblocks.
For many applications this straightforward approach is adequate. There are, however, circumstances when it is desirable to produce HDL whose organization does not exactly mirror that of the HLMS design from which was derived, and/or to adjust the order in which entities are generated for certain blocks.
The present invention may address one or more of the above issues.